0.71 [smf, Ryan Holtz, R Belmont, Farfetch, The Zinc Team]
TODO :
- Random draw list corruption in soul edge v2 & dunkmania.
- Soul edge, dunk mania & prime goal ex try to access joypads/memory cards. It is unknown what they would do if they found one.
- Pocket Racer can't enter service menus with proper C76 hookup, runs 60 FPS when it looks like it should be 30.

NOTES :
- Driver: smf & Ryan Holtz with help from R. Belmont and The Zinc Team and board notes are from Guru.
- Not Dumped Boards: Don Bear Near (Namco 1996), Point Blank 3 (Namco 2001), Soul Edge Ver. III (Namco 1996), Tekken Ver.C (Namco 1995) and Tekken II Ver.C (Namco 1995). If you can help with the remaining undumped S11 games, please contact http://www.mameworld.net/gurudumps/comments.html

BUGS :
- souledge, souledga, dunkmnia: Random draw list corruption. Source (ID 02370)

WIP :
- 0.136u3: Namco System 11 driver now use real C76 BIOS for audio and I/O [R. Belmont, Olivier Galibert, Guru]. Added dipswitches 'TDIP1' - 'TDIP8'.
- 31st January 2010: R. Belmont - I reworked the Namco System 11 driver to use the real "C76" MCU ROM dump that was trojaned by Olivier Galibert. I don't notice any real difference between now and the previous hacky solution using Prop Cycle's program as a splint, but at least now it's properly documented.
- 0.125u7: Fabio Priuli updated most Namco systems + a couple of old drivers sharing the input handling.
- 0.124u3: PSX core updates [smf]: Removed casts and removed unnecessary decoding from NCLIP. Added signed values to PAIR & PAIR64. Renamed PAIR64.lw to PAIR64.q. Tidied up DPCS, improved flag calculation and added support for lm/sf fields. Added sf/lm support to INTPL, improved flag calculation & calculates correct RGB. Fixed calculation of bit 31 of GTE FLAG register, when writing to it directly. Added lm mode to OP and fixed the calculation. Added lm mode to SQR.
- 0.124u2: PSX updates [smf]: Fixed the SR masks for MTC0. Added ability to test the instruction/data cache ram. The scratchpad and BIU register are now handled internally to the CPU. All writes are performed with masks. SWL/SWR used to be implemented with two writes ( one byte and one word ) when writing three bytes, now it only ever performs one. Byte and Word writes use masks as they leave the rest of the register on the bus, which can be picked up by larger registers. The read/write functions to use are cached when the SR bits are updated, as are the bad address masks. Added coprocessor 1 & 3 support, though they don't do anything useful. All loads now go through the delay pipeline, a lwl/lwr will grab the value out of the pipeline if it's updating the same register. Added undocumented behaviour of BLEZ/BGTZ. The comparison for zero can be changed by specifying an alternate register in the RT field ( the documentation says you should always use register 0 ). Restricted to 16 COP0 registers & generate an exception if any of the 5 for the MMU are used. Added BCF/BCT instructions, although I have found no conditions that affect them yet. Generates an exception if any MMU instructions are executed. Sets the CE instruction for all exceptions, not just those involving a coprocessor. The bits of the opcode that specify the coprocessor are grabbed no matter what the instruction. Added TAR register and BT bit in SR. When an exception occurs during a branch, BT determines whether it was taken or not. The TAR register gets set to the destination of the branch. Fixed the BD bit when you are in a branch delay slot and you didn't take the branch, this shows up in the pipeline as !pc. Fixed branches within a branch delay slot. Multiply & divide instructions can be aborted if you write to HI/LO before reading the result. Added data breakpoints, you don't appear to be able to set breakpoints on any of the addresses internal to the CPU. Multiply/divide/GTE instructions can execute when an exception is taken, although the EPC indicates that it hasn't. The BIOS avoids rerunning GTE instructions as they are destructive, so you have to make sure they run. Added bus error handling, PSXCPU is limited to 8mb of ram & any access outside this range will trigger an exception. I believe this is to be an internal limit. Added CXD8661R as a specific CPU type, System 12 appears to allow more than 8mb of ram & it's possible that this is different. Mapped out all instructions to either generate an exception or ignore bits. Updated the disassembler to match the decoding. Fixed disassembling of branch instructions in a branch delay slot. Lui checks for a ori/addiu following and will show you the result. Added step over/out support. Fixed standalone disassembler. Fixed SZ0 truncation. Fixed IRGB truncation and conversion to IR1/IR2/IR3. Added IR1/IR2/IR3 saturation when calculating ORGB. Fixed OTZ sign extension. Fixed reading from SXYP. Fixed reading from IRGB. Fixed writing to LZCR. Fixed sign extension of GTE control registers. Fixed writing to FLAG. Fixed flag calculation in F macro and fixed avsz3 & avsz4 flag & otz calculation.
- 0.123u1: Added 'Service Mode' dipswitch.
- 0.122u7: Switched namcos11/namcos12 over to memory_configure_bank / memory_set_bank [smf].
- 0.122u6: First pass at fixing the CPU clock speeds on the playstation based hardware. The internal divide in the CPU core has been set to 4 as we have no wait states, incorrect DMA timing, no gpu timing, no DMA bus stealing and no gte timing [smf]. Changed PSX CPU clock speed to 67737600 Hz.
- 16th January 2008: smf - The clockspeed of the PSX based games in MAME has always been a little on the low side. Mainly to make up for the lack of cache emulation and bus contention, also partly because the GTE timing isn't emulated yet. Due to the recent attention to crystals, there has been some investigation as to what the real clock speed should be. Thanks to Guru's probing we are able to say for definate what is going on. The CPU has an internal divider and on the majority of boards is fed a 67.7376MHz clock. I have currently got MAME to report this frequency, with an internal divider of 4 to keep it roughly the same as before ( it should be 2 but I'll leave that until the rest of the timing issues are sorted ). Some information has been floating around for a while that has never been confirmed & now seems to be a good time. The 67MHz clock doesn't appear on the namco system 12 or the later system 10 boards. It appears they have their own higher rated part. System 12 runs on a 100MHz clock, while system 10 runs on a 101.4912MHz clock. So system 12 being faster has been elevated from rumour, to probable. The GPU clock is the same across all hardware. I'd have thought they'd have done something about that, especially as all the system 12 games like to run in interlace. Maybe it's more efficient or has faster ram, we'll leave that one for another day.
- 0.111u5: Nathan Woods updated the PSX GPU video driver to use the new BITMAP_ADDR* macros instead of using the line[] array.
- 0.110: smf and Aaron Giles fixed crash when resetting PSX games.
- 0.105u2: Nathan Woods fixed the 'Fatal error: Invalid data type' crash in namcos11 driver.
- 0.104u2: Changed CPU2 from M37710 to M37702 (16384000 Hz).
- 0.103u2: Fixed some Endian issues in the Namco drivers [R. Belmont].
- 0.101u4: smf updated PSX core to new save state and disassembler interfaces.
- 0.100: R. Belmont fully shared the sound part of the MCU RAM for System 11. This allows games to read back the song names and fixes the sound test menu in Tekken and Tekken 2.
- 0.99u10: R. Belmont fixed incorrect voices and swapped stereo in System 11/12 games.
- 0.99u9: Added sndhrdw\namcoc7x.c. Major Namco sound improvements [R. Belmont]: Added emulated sound and music to all NB-1, NB-2 and System 11 games, using Prop Cycle's MCU BIOS (pr1data.8k) as a substitute until the original can be trojaned or otherwise obtained. Hooked it up for plain System 22 games as well, but they're not interested in passing down proper commands for some reason. Speed-cheated all instances of the M37710/C352 sound system so CPU requirements don't go up much. This also helped back off the requirements a hair for Prop Cycle and Time Crisis. C352 now sets output pitch correctly by input clock. Added M37710 (16384000 Hz) and C352 (16384000 Hz) stereo sound.
- 0.97u3: Improvements to the PSX CPU core [smf]: Correct behaviour for a branch in a delay slot, added BIOS and syscall logging of all known functions & their parameters (writing to file descriptor 1 or putchar will output to the console), fixed disassembly of gte instructions and dismips.mak
- 0.92: Fixed rom names.
- 0.84: darkcoder fixed the Speaker Puncturing Unit in the PSX games. R. Belmont and smf fixed several endian issues in the PSX-related drivers.
- 0.78: Brian Troha added GP-13 board layout informations to the Namco System 11 driver.
- 8th November 2003: smf did some more cleanup on the Namco System 11 driver.
- 1st November 2003: smf did some changes to the GPU DMA in the Namco System 11 driver and added some Namco System 12 ROMs, but they don't work at all yet.
- 23rd October 2003: smf sent in a small update to the Namco System 11 driver cleaning up things.
- 22nd October 2003: smf sent in another update to the Namco System 11 driver, improving the MDEC decoding and enabling Soul Edge (Ver. A) since it seems to work fine.
- 23rd July 2003: Brian Troha fixed some ROM names in the Namco System 11 driver.
- 0.71u1: smf cleaned up and fixed filenames in Namco System 11 driver.
- 5th July 2003: smf cleaned up the Namco System 11 driver and updated the documentation in it.
- 0.71: Added namcos11.c driver.

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